54 lines
1003 B
Systemverilog
54 lines
1003 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface Ifc;
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logic req, grant;
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logic [7:0] addr, data;
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endinterface
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class Cls;
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virtual Ifc bus;
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int m_i;
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function new(virtual Ifc s, int i);
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bus = s;
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m_i = i;
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endfunction
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task request();
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bus.req <= 1'b1;
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endtask
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task wait_for_bus();
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@(posedge bus.grant);
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endtask
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endclass
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module devA (Ifc s);
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endmodule
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module devB (Ifc s);
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endmodule
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module top;
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Ifc s14[1:4] ();
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devA a1 (s14[1]);
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devB b1 (s14[2]);
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devA a2 (s14[3]);
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devB b2 (s14[4]);
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Ifc s65[6:5] ();
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devA a3 (s65[5]);
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devB b3 (s65[6]);
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initial begin
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Cls t14[1:4];
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Cls t65[6:5];
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t14[1] = new(s14[1], 1);
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t14[2] = new(s14[2], 2);
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t14[3] = new(s14[3], 3);
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t14[4] = new(s14[4], 4);
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t65[5] = new(s65[5], 5);
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t65[6] = new(s65[6], 6);
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end
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endmodule
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