30 lines
658 B
Systemverilog
30 lines
658 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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interface intf
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(input wire clk,
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input wire rst);
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modport intf_modp (input clk, rst);
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endinterface
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module sub
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// verilator public_on
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(intf.intf_modp intf_port);
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always @ (posedge intf_port.clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// verilator public_off
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endmodule
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module t(clk);
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input clk /*verilator public*/ ;
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logic rst;
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intf the_intf (.clk, .rst);
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sub the_sub (.intf_port (the_intf));
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endmodule
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