74 lines
1.8 KiB
Systemverilog
74 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface Bus1;
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logic [15:0] data;
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endinterface
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interface Bus2;
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logic [15:0] data;
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endinterface
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interface Bus3;
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logic [15:0] data;
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endinterface
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module t_controlflow;
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logic clk = 0;
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integer cyc = 0;
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Bus1 intf1();
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Bus2 intf2();
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Bus3 intf3(), intf4();
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virtual Bus1 vif1 = intf1;
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virtual Bus2 vif2 = intf2;
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virtual Bus3 vif3 = intf3, vif4 = intf4;
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// Finish on negedge so that $finish is last
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always @(negedge clk) begin
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if (cyc >= 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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function void assign_to_intf3();
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intf3.data = 'hcafe;
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endfunction
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead;
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else vif2.data = 'hbeef;
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if (cyc == 1 || cyc == 3 || cyc == 5) begin
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if (cyc < 3) intf3.data = 'hfafa;
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intf4.data = 'hface;
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end
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if (cyc == 7) begin
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intf4.data = 'hcafe;
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end
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if (cyc == 9) begin
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assign_to_intf3;
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intf4.data = 'hdeaf;
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end
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end
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always @(vif1.data) begin
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$write("[%0t] vif1.data==%h\n", $time, vif1.data);
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end
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always @(intf2.data) begin
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$write("[%0t] intf2.data==%h\n", $time, intf2.data);
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end
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always @(vif3.data) begin
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$write("[%0t] vif3.data==%h\n", $time, vif3.data);
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end
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always @(intf4.data) begin
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$write("[%0t] intf4.data==%h\n", $time, intf4.data);
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end
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initial begin
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repeat (20) #5ns clk = ~clk;
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end
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endmodule
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