verilator/test_regress/t/t_interface_virtual_sched_i...

21 lines
535 B
Plaintext

[0] intf1.inc==00000000
[0] vif2.inc==00000001
[5000] intf1.inc==00000001
[10000] vif2.inc==00000002
[15000] intf1.inc==00000002
[20000] vif2.inc==00000003
[25000] intf1.inc==00000003
[30000] vif2.inc==00000004
[35000] intf1.inc==00000004
[40000] vif2.inc==00000005
[45000] intf1.inc==00000005
[50000] vif2.inc==00000006
[55000] intf1.inc==00000006
[60000] vif2.inc==00000007
[65000] intf1.inc==00000007
[70000] vif2.inc==00000008
[75000] intf1.inc==00000008
[80000] vif2.inc==00000009
[85000] intf1.inc==00000009
*-* All Finished *-*