61 lines
1.0 KiB
Systemverilog
61 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface If;
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logic [31:0] inc;
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endinterface
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module top;
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logic clk = 0;
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logic [31:0] inc1 = 0;
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logic [31:0] inc2 = 0;
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int cyc = 0;
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If intf1();
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If intf2();
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virtual If vif1 = intf1;
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virtual If vif2 = intf2;
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// assign vif1.inc = inc1;
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always @(posedge clk) begin
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vif1.inc <= inc1;
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end
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assign intf2.inc = inc2;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc >= 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(intf1.inc) begin
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$write("[%0t] intf1.inc==%h\n", $time, intf1.inc);
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end
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always @(vif2.inc) begin
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$write("[%0t] vif2.inc==%h\n", $time, vif2.inc);
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end
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initial begin
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repeat (30) #5ns clk = ~clk;
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end
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initial begin
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inc1 = 1;
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inc2 = 1;
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repeat (8) begin
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#10ns;
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inc1 = inc1 + 1;
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inc2 = inc2 + 1;
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end
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end
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endmodule
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