48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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interface Bus;
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logic [15:0] data;
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endinterface
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module t;
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Bus intf1(), intf2();
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virtual Bus vif1 = intf1, vif2 = intf2;
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task assign_to_vif2();
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if ($c("0")) return;
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#1 vif2.data = 'hfafa; #1;
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endtask
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initial forever begin
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intf1.data = 'hdead;
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if ($c("1")) begin
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#1 vif2.data = 'hbeef; #1;
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end
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intf1.data = 'hcafe;
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if ($c("0")); else begin
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#1 vif2.data = 'hface; #1;
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end
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intf1.data = 'hfeed;
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while ($time < 5) begin
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#1 vif2.data = 'hdeed; #1;
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end
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intf1.data = 'hdeaf;
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assign_to_vif2;
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intf1.data = 'hbebe;
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#1 $write("*-* All Finished *-*\n");
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$finish;
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end
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always @(vif1.data) begin
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if ($time < 9) $write("[%0t] vif1.data==%h\n", $time, vif1.data);
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end
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always @(intf2.data) begin
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if ($time < 9) $write("[%0t] intf2.data==%h\n", $time, intf2.data);
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end
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endmodule
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