7 lines
368 B
Plaintext
7 lines
368 B
Plaintext
%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface.
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: ... note: In instance 't'
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17 | wire wbad = sub.a;
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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