20 lines
1.3 KiB
Plaintext
20 lines
1.3 KiB
Plaintext
%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignment '=' in sequential logic process
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: ... Suggest using delayed assignment '<='
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24 | sync_blk = 1'b1;
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| ^
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... For warning description see https://verilator.org/warn/BLKSEQ?v=latest
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... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
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%Warning-BLKSEQ: t/t_lint_blksync_bad.v:25:17: Blocking assignment '=' in sequential logic process
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: ... Suggest using delayed assignment '<='
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25 | sync_blk2 = 1'b1;
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| ^
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%Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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31 | combo_nblk <= 1'b1;
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| ^~
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... For warning description see https://verilator.org/warn/COMBDLY?v=latest
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See https://verilator.org/warn/COMBDLY?v=latest before disabling this,
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else you may end up with different sim results.
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%Error: Exiting due to
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