57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk, reset_l, in, enable
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);
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input clk;
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input reset_l;
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input in;
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input enable;
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logic ok1 = 1;
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logic ok2 = 1;
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logic ok3 = ok2;
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initial begin
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ok1 = 1;
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end
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//== Faulty example
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logic flop_out = 1; // <--- Warning
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always @(posedge clk, negedge reset_l) begin
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if (enable) begin
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flop_out <= ~in; // <--- Use of initialized
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end
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end
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//== Fixed example
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logic flop2_out;
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always @(posedge clk, negedge reset_l) begin
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if (!reset_l) begin
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flop2_out <= '1; // <--- Added reset init
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end
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else if (enable) begin
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flop2_out <= ~in;
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end
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end
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// Combo version
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logic bad_comb = 1; // but this is not fine
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always @* begin
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bad_comb = ok2;
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end
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wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3};
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endmodule
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