34 lines
931 B
Systemverilog
34 lines
931 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns / 1ps
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module sub;
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time t_ok1 = 9ns; // > 1ns units
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time t_bad1 = 9.001ns; // < 1ns units
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time t_bad2 = 9.999ns; // < 1ns units
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time t_ok2 = 9.001us; // > 1ns units
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time t_bad3 = 9ps; // < 1ns units
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realtime rt_ok10 = 9.001ns; // < 1ns units
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realtime rt_ok11 = 9ps; // < 1ns units
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integer i_ok20 = 23.0; // No warning
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integer i_bad21 = 23.1;
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initial begin
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int i;
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i = $signed(1.0); // Error, doesn't support real, not just warning
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i = $unsigned(1.0); // Error, doesn't support real, not just warning
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i = {1.2, 1.3}; // Error, doesn't support real, not just warning
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i = {6{1.2}}; // Error, doesn't support real, not just warning
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end
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endmodule
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