24 lines
660 B
Systemverilog
24 lines
660 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic my_vec [4];
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logic bool;
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int count;
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initial begin
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my_vec = '{1, 0, 1, 0};
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count = $countones(my_vec); // Bad, must be bit vector
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count = $countbits(my_vec, '0); // Bad, must be bit vector
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bool = $onehot(my_vec); // Bad, must be bit vector
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bool = $onehot0(my_vec); // Bad, must be bit vector
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bool = $isunknown(my_vec); // Bad, must be bit vector
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$stop;
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end
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endmodule
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