43 lines
953 B
Systemverilog
43 lines
953 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t;
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// Issue #5972
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reg clk;
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reg signed [28:28] in1;
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reg signed [21:8] reg_10;
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// verilator lint_off WIDTHEXPAND
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always @(negedge clk) begin
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// Issue #5972
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reg_10[14:8] <= {1'b1, ~((in1[28:28] & ~(in1[28:28])))};
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end
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initial begin
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clk = 1;
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in1 = 1'b0;
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reg_10 = '0;
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#2;
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clk = 0;
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#2;
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`checkh(reg_10, 3);
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in1 = 1'b1;
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clk = 1;
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#2;
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clk = 0;
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#2;
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`checkh(reg_10, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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