79 lines
1.7 KiB
Systemverilog
79 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t;
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wire signed [21:10] out0;
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sub sub (
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.out0(out0)
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);
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sub2 sub2 ();
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string s;
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initial begin
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#20;
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// Bug with sformat, so can't just number-compare
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s = $sformatf("out0=%0d", out0);
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`checks(s, "out0=-12");
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if (out0 > 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (out0);
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reg signed [27:20] reg_4;
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output wire [21:10] out0;
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initial begin
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#1;
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reg_4 = 0;
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end
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wire [11:0] w55;
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wire [11:0] w23;
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// verilator lint_off WIDTHEXPAND
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assign w55 = ~reg_4[20];
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// verilator lint_on WIDTHEXPAND
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assign { w23[3], w23[1:0] } = 3'h0;
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assign { w23[11:4], w23[2] } = { w55[11:4], w55[2] };
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assign out0 = w23;
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endmodule
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module sub2;
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reg [27:5] in0;
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reg [26:11] in1;
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wire [24:14] wire_0;
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wire [26:5] out1;
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wire w085;
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wire w082;
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wire [10:0] w092;
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wire [9:0] w028;
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string s;
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initial begin
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in0 = 6902127;
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in1 = 10000;
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#10;
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s = $sformatf("out0=%0d", out1);
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`checks(s, "out0=0");
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end
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assign w028 = ~ { 9'h000, in0[23] };
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assign w092[1] = 1'h0;
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assign { w092[10:2], w092[0] } = w028;
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assign wire_0 = w092;
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assign w082 = | wire_0[18:17];
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assign w085 = w082 ? in1[11] : 1'h0;
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assign out1 = { 21'h000000, w085 };
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endmodule
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