23 lines
677 B
Systemverilog
23 lines
677 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0);
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module top(out35);
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output wire [2:0] out35;
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wire signed [2:0] wire_4;
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assign wire_4 = 3'b011;
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assign out35 = (wire_4 >>> 36'hffff_ffff_f);
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initial begin
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#10;
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`checkd(out35, '0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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