24 lines
707 B
Systemverilog
24 lines
707 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Based on ivtest's pr540.v by Steve Williams.
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module t;
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bit fail = 0;
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bit abort = 0;
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initial begin
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abort = 1; // Set here so it's non-constant, otherwise ifs gets folded
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begin: block
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if (abort) disable block;
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fail = 1; // Don't try to move this in order to merge the 2 ifs
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if (abort) $display("unreachable");
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end
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if (fail) $error("block disable FAILED");
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$write("*-* All Finished *-*\n");
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$finish(0);
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end
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endmodule
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