73 lines
2.2 KiB
Systemverilog
73 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [31:0] cyc = 0;
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reg [31:0] sameAsCycButCantBeOptimized_0;
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reg [31:0] sameAsCycButCantBeOptimized_1;
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reg [31:0] sameAsCycButCantBeOptimized_2;
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// 'x' has both blocking and non-blocking update, with the blocking
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// update in **combinational** logic
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reg [1:0] x = 2'b00;
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// '{y1, y0}' should have exactly the same value as 'x', at all times
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reg y0 = 1'b0;
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reg y1 = 1'b0;
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// 'z[0]' should equal '{8{x[0]}', 'z[1]' should equal '{8{x[1]}}'
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// verilator lint_off BLKANDNBLK
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reg [1:0][7:0] z;
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// verilator lint_on BLKANDNBLK
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// 'pair.a' should equal 'x[0]', 'pair.b' should equal 'x[1]'
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// verilator lint_off BLKANDNBLK
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struct {
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logic a;
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logic b;
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} pair = '{a: 1'b0, b: 1'b0};
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// verilator lint_on BLKANDNBLK
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assign x[0] = cyc[0];
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assign y0 = sameAsCycButCantBeOptimized_0[0];
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always_comb begin
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for (int i = 0; i < 8; ++i) z[0][i] = sameAsCycButCantBeOptimized_1[0];
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end
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assign pair.a = sameAsCycButCantBeOptimized_2[0];
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always @(posedge clk) begin
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$display("cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x", cyc, cyc, x[1], x[0], y1, y0, z[1], z[0]);
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`check(x[0], cyc[0]);
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`check(x[1], cyc[0]);
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`check(y0, cyc[0]);
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`check(y1, cyc[0]);
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`check(z[0], {8{cyc[0]}});
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`check(z[1], {8{cyc[0]}});
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`check(pair.a, cyc[0]);
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`check(pair.b, cyc[0]);
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x[1] <= ~x[1];
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y1 <= ~y1;
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for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i];
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pair.b <= ~pair.b;
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cyc = cyc + 1;
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sameAsCycButCantBeOptimized_0 = cyc;
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sameAsCycButCantBeOptimized_1 = cyc;
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sameAsCycButCantBeOptimized_2 = cyc;
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if (cyc == 99) begin
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$display(x);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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