73 lines
1.5 KiB
Systemverilog
73 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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module t;
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reg clk = 1'b1;
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reg reset = 1'b1;
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reg aw_valid = 1'b0;
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reg w_valid = 1'b0;
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reg r_valid;
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reg [31:0] addr [1:0];
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reg [7:0] len [1:0];
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always #5 clk = ~clk;
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initial begin
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#5; // Align with negedge clk
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#20;
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`checkh(addr[0], 32'h0000_0000);
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reset = 1'b0;
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#20;
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`checkh(addr[0], 32'h0000_0000);
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aw_valid = 1'b1;
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w_valid = 1'b1;
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#10;
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`checkh(addr[0], 32'h4444_4444);
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aw_valid = 1'b0;
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#10;
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`checkh(addr[0], 32'h2222_2222);
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w_valid = 1'b0;
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#10;
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`checkh(addr[0], 32'h2222_2222);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk) begin
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if (reset) begin
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r_valid <= 0;
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end
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else begin
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if (r_valid) begin
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addr[0] <= 32'h11111111;
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len[0] <= len[0] - 1;
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end
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if (w_valid) begin
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addr[0] <= 32'h22222222;
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end
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if (aw_valid) begin
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addr[0] <= 32'h33333333;
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len[0] <= 8'hff;
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if (w_valid)
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addr[0] <= 32'h44444444;
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end
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end
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end
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endmodule
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