23 lines
549 B
Systemverilog
23 lines
549 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef enum logic [2:0] {
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TWO = 2,
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THREE = 3
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} enum_t;
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endpackage
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module t;
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localparam L_TWO = pkg::TWO;
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initial begin
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if (L_TWO != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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