62 lines
1.4 KiB
Systemverilog
62 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module gymhnulbvj (in5, clock_10, clock_12, out18);
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input wire [23:22] in5;
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wire [29:1] wire_4;
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reg reg_35;
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output wire out18;
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input wire clock_10;
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input wire clock_12;
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// verilator lint_off WIDTH
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assign wire_4 = ~ in5[22];
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assign out18 = reg_35 ? 0 : !(!(~(wire_4[6:5] | 8'hc6)));
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// verilator lint_on WIDTH
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always @(posedge clock_10 or posedge clock_12) begin
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if (clock_12) begin
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reg_35 <= 0;
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end
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else begin
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// verilator lint_off WIDTH
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reg_35 <= wire_4;
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// verilator lint_on WIDTH
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end
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end
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endmodule
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module t;
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reg [23:22] in5;
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reg clock_10 = 0;
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reg clock_12 = 0;
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wire out18;
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gymhnulbvj uut (
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.in5(in5),
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.clock_10(clock_10),
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.clock_12(clock_12),
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.out18(out18)
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);
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initial begin
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$monitor("[%0t] in5=%d clock_10=%d clock_12=%d out18=%d", $time, in5, clock_10, clock_12, out18);
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in5 = 2'b00;
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#5 clock_12 = 1;
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#5 clock_12 = 0;
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#5 clock_10 = 1;
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#5 clock_10 = 0;
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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