32 lines
629 B
Systemverilog
32 lines
629 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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static function int get(int x);
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return x;
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endfunction
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endclass
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class Bar;
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static function int get;
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return 42;
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endfunction
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endclass
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class Qux #(type Tfoo, type Tbar);
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static function int get();
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return Tfoo::get(Tbar::get());
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endfunction
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endclass
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module t;
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initial begin
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if (Qux#(Foo, Bar)::get() != 42) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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