29 lines
693 B
Systemverilog
29 lines
693 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/);
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initial begin
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bit q1[$] = {1'b1};
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bit q2[$];
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bit q3[$];
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bit [1:0] d1[] = {2'b10};
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bit [1:0] d2[];
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// TODO: queue streaming support broke assignment like this.
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// It's something to do witih computeCastable and V3Width.cpp
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// q2 = {q1};
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// if (q2[0] != 1) $stop;
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q3 = q1;
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if (q3[0] != 1) $stop;
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d2 = {2'b11};
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if (d2[0] != 2'b11) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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