28 lines
507 B
Systemverilog
28 lines
507 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int x = 1;
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endclass
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task init_set_2 (output Cls c);
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c = new;
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c.x = 2;
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endtask
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module t (/*AUTOARG*/);
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initial begin
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Cls cls_q[$];
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init_set_2(cls_q[0]);
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if (cls_q[0].x != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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