76 lines
1.6 KiB
Systemverilog
76 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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typedef enum int {
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RANDOMIZED = 20
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} enumed_t;
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class Base;
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int m_pre;
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rand enumed_t r;
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int m_post;
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function void pre_randomize;
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`checkd(m_pre, 0);
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`checkd(r, enumed_t'(0));
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`checkd(m_post, 0);
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m_pre = 10;
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endfunction
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function void post_randomize;
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`checkd(m_pre, 10);
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`checkd(r, RANDOMIZED);
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`checkd(m_post, 0);
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m_post = 30;
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endfunction
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endclass
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class Cls extends Base;
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int m_cpre;
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int m_cpost;
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function void pre_randomize;
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m_cpre = 111;
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super.pre_randomize();
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endfunction
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function void post_randomize;
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m_cpost = 222;
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super.post_randomize();
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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int rand_result;
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c = new;
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rand_result = c.randomize();
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`checkd(rand_result, 1);
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`checkd(c.m_pre, 10);
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`checkd(c.m_cpre, 111);
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`checkd(c.r, RANDOMIZED);
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`checkd(c.m_post, 30);
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`checkd(c.m_cpost, 222);
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c = new;
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rand_result = c.randomize() with { r == RANDOMIZED; };
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`checkd(rand_result, 1);
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`checkd(c.m_pre, 10);
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`checkd(c.m_cpre, 111);
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`checkd(c.r, RANDOMIZED);
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`checkd(c.m_post, 30);
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`checkd(c.m_cpost, 222);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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