40 lines
892 B
Systemverilog
40 lines
892 B
Systemverilog
// DESCRIPTION: Verilator: Confirm x randomization stability
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef logic [85:0] big_t;
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localparam big_t foo = big_t'(8.531630271583128e+16);
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big_t bar;
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int cyc;
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real some_real;
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initial begin
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cyc = 0;
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some_real = 5.123;
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end
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always_comb bar = big_t'(some_real);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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some_real <= some_real * 1.234e4;
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if (cyc == 6) begin
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if (foo != 86'd85316302715831280) $stop();
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if (bar != 86'd18089031459271914704338944) $stop();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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