23 lines
486 B
Systemverilog
23 lines
486 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(
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input clk1,
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input clk2,
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output logic multidriven);
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wire [1:0] trunced = 5'b11111; // Warned
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always @ (posedge clk1)
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multidriven <= '1;
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always @ (posedge clk2)
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multidriven <= '0;
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endmodule
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module t; // BAD duplicate
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endmodule
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