57 lines
1.3 KiB
Systemverilog
57 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam int ITERATIONS = 5;
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localparam int N = 227;
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logic [N-1:0] gclk = {N{1'b0}};
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// Not actually used, but creates an extra internal trigger
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export "DPI-C" function toggle;
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function void toggle();
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gclk = ~gclk;
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endfunction
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int cyc = 0;
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always @(posedge clk) begin
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if (~|gclk) begin
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gclk[0] = 1'b1;
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end else begin
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gclk = {gclk[N-2:0], gclk[N-1]};
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end
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cyc <= cyc + 32'd1;
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if (cyc == ITERATIONS*N - 1) begin
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$display("cyc");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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for (genvar n = 0; n < N; n++) begin : gen
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int cnt = 0;
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always @(posedge gclk[n]) cnt <= cnt + 1;
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int cnt_plus_one;
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always_comb cnt_plus_one = cnt + 1;
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final begin
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`checkh(cnt_plus_one, ITERATIONS + 1);
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end
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end
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endmodule
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