21 lines
616 B
Systemverilog
21 lines
616 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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$sdf_annotate("file.sdf");
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$sdf_annotate("file.sdf",);
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$sdf_annotate("file.sdf", t);
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// TArguments are all optional, so test more exhaustively
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$sdf_annotate("file.sdf", t, "config_file", "log_file", "mtm_spec", "scale_factors",
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"scale_type");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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