21 lines
1.4 KiB
Plaintext
21 lines
1.4 KiB
Plaintext
%Error: t/t_select_bad_width0.v:15:21: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
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: ... note: In instance 't'
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15 | int part = val[left +: ZERO];
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:21: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
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: ... note: In instance 't'
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15 | int part = val[left +: ZERO];
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| ^
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... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
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... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
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%Error: t/t_select_bad_width0.v:17:17: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
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: ... note: In instance 't'
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17 | part = val[left -: ZERO];
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| ^
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%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:17:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
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: ... note: In instance 't'
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17 | part = val[left -: ZERO];
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| ^
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%Error: Exiting due to
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