29 lines
767 B
Systemverilog
29 lines
767 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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class cls;
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int m_field;
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endclass
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module t();
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cls inst[2];
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initial begin
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// Loop (even just 1 iteration) is needed to reproduce the error
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for (int i = 0; i < 2; ++i) begin
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inst[i] = new();
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inst[i].m_field = i;
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end
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for (int i = 0; i < 2; ++i) begin
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if (inst[i].m_field != i) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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