28 lines
685 B
Systemverilog
28 lines
685 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// verilator lint_off WIDTH
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// verilator lint_off IMPLICIT
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wire [22:0] w274;
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wire w412;
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wire w413;
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wire w509;
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assign w104 = ! w509;
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assign w201 = w258 > 12'hab7;
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assign w204 = 7'h7f <= w104;
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wire [11:0] w258 = 3'h3 || w274;
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assign w538 = w412 ? out21 : w201;
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wire [16:0] w539 = w413 ? w538 : 17'h00570;
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wire [21:5] out21 = w204;
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assign out51 = w539[0];
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initial begin
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$display("%0d", out51);
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end
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endmodule
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