45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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specify
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specparam tdevice_PU = 3e8;
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specparam Tdelay11 = 1.1;
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// verilator lint_off MINTYPMAXDLY
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specparam Tmintypmax = 1.0:1.1:1.2;
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specparam PATHPULSE$a$b = (3.0:3.1:3.2, 4.0:4.1:4.2);
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specparam randomize = 1; // Special parser corner-case
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endspecify
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// Support in other simulators is limited for module specparams
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specparam Tmod34 = 3.4, Tmod35 = 3.5; // IEEE 6.20.5 allowed in body
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// Support in other simulators is limited for ranged specparams
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specparam [5:2] Tranged = 4'b1011;
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localparam real PATHPULSE$normal$var = 6.78;
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reg PoweredUp;
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wire DelayIn, DelayOut;
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assign #tdevice_PU DelayOut = DelayIn;
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initial begin
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PoweredUp = 1'b0;
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#tdevice_PU PoweredUp = 1'b1;
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if (Tdelay11 != 1.1) $stop;
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`ifdef VERILATOR
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if (Tmintypmax != 1.1) $stop;
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if (PATHPULSE$a$b != 3.1) $stop;
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`endif
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if (Tranged != 4'b1011) $stop;
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if (Tmod34 != 3.4) $stop;
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if (Tmod35 != 3.5) $stop;
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if (PATHPULSE$normal$var != 6.78) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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