24 lines
593 B
Systemverilog
24 lines
593 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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module t_std_randomize_bad1;
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bit [3:0] a;
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function int run();
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int success;
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success = std::randomize(a + 1); // ERROR: argument is not a variable
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return success;
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endfunction
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initial begin
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int ok, x;
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ok = run();
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void'(std::randomize(null));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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