19 lines
438 B
Systemverilog
19 lines
438 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [31:0] packed_data_32;
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byte byte_in [4];
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logic [ 3:0] x = 4'($random());
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initial begin
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packed_data_32 = {<<$random{byte_in}};
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packed_data_32 = {<<x{byte_in}};
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end
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endmodule
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