27 lines
652 B
Systemverilog
27 lines
652 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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integer cyc = 0;
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logic [2:0] cmd_ready;
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logic cmd_ready_unpack[3];
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logic cmd_ready_o[3];
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assign cmd_ready = {1'b1, clk, ~clk};
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assign cmd_ready_unpack = {<<{cmd_ready}};
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assign cmd_ready_o = cmd_ready_unpack;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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