61 lines
1.3 KiB
Systemverilog
61 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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string str;
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} str_s;
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class c;
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string str;
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function new();
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str = "foo";
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endfunction
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function string get_str();
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return str;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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string str = "bar";
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function string get_str();
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return str;
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endfunction
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initial begin
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c o = new;
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str_s st = '{"qux"};
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string sc = {"foo", "bar"};
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// read
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if (str[0] != "b") $stop;
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if (get_str()[1] != "a") $stop;
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if (str[3] != "\0") $stop;
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if (st.str[2] != "x") $stop;
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if (st.str[99] != "\0") $stop;
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if (o.str[0] != "f") $stop;
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if (o.get_str()[1] != "o") $stop;
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if (o.str[-1] != "\0") $stop;
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if (sc[2] != "o") $stop;
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if ($sformatf("foo%s", "bar")[3] != "b") $stop;
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if (sc[-1] != "\0") $stop;
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if (sc[6] != "\0") $stop;
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if (sc[99] != "\0") $stop;
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// write
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sc[5] = "z";
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if (sc != "foobaz") $stop;
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o.str[0] = "b";
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if (o.str != "boo") $stop;
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st.str[2] = "z";
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if (st.str != "quz") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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