25 lines
634 B
Systemverilog
25 lines
634 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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logic [31:0] tmp;
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logic [31:0] tmp2;
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logic [31:0] tmp3;
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initial begin
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tmp = 0;
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$monitor("[%0t] monitor0 %h", $time, tmp);
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while (tmp < 32) begin
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tmp = tmp + 1;
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if ((tmp % 5) == 1) begin
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tmp = tmp + 2;
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tmp = tmp + 1;
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end
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#1;
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end
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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