38 lines
1.2 KiB
Systemverilog
38 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t;
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int cfg_file, f_stat;
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reg [8*8:1] fname;
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int index;
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int count;
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initial begin
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cfg_file = $fopen("t/t_sys_file_scan2.dat", "r");
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f_stat = $fscanf(cfg_file, "%s", fname);
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`checkd(f_stat, 1);
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`checks(fname, "vec");
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f_stat = $fscanf(cfg_file, "%d", index);
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`checkd(f_stat, 1);
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`checkd(index, 6163);
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f_stat = $fscanf(cfg_file, "%d", count);
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`checkd(f_stat, 1);
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`checkd(count, 16);
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//eof
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f_stat = $fscanf(cfg_file, "%s", fname);
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`checkd(f_stat, -1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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