32 lines
595 B
Systemverilog
32 lines
595 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk;
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int a, b;
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always #10 clk = ~clk;
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initial begin
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$monitor("[%0t] a=%0d b=%0d", $time, a, b);
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#1; // So not on clock edge
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#100;
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a = 10;
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#10;
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b = 20;
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#10;
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a = 11;
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#10;
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b = 22;
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#100;
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#10;
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$monitoroff;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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