95 lines
2.1 KiB
Systemverilog
95 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface addsub_ifc;
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logic [7:0] a, b;
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logic doAdd0;
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logic clk;
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logic rst_n;
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logic [7:0] result;
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logic overflow;
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endinterface
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module adder_sub_8bit
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(
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input logic clk,
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input logic rst_n,
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input logic [7:0] a,
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input logic [7:0] b,
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input logic doAdd0,
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output logic [7:0] result,
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output logic overflow
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);
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logic [7:0] b_modified;
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logic [8:0] temp_result;
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assign b_modified = doAdd0 ? b : ~b + 8'b1;
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always_comb begin
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temp_result = {1'b0, a} + {1'b0, b_modified};
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result <= 8'h0;
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overflow <= 1'b0;
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end else begin
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result <= temp_result[7:0];
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overflow <= (a[7] == b_modified[7] && result[7] != a[7]);
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end
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end
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endmodule
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module t;
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addsub_ifc dut_ifc();
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adder_sub_8bit dut
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(
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.clk(dut_ifc.clk),
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.rst_n(dut_ifc.rst_n),
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.a(dut_ifc.a),
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.b(dut_ifc.b),
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.doAdd0(dut_ifc.doAdd0),
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.result(dut_ifc.result),
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.overflow(dut_ifc.overflow)
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);
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initial begin
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dut_ifc.clk = 0;
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forever #5 dut_ifc.clk = ~dut_ifc.clk;
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end
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initial begin
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dut_ifc.rst_n = 0;
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dut_ifc.a = 8'h0;
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dut_ifc.b = 8'h0;
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dut_ifc.doAdd0 = 1'b1;
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#10 dut_ifc.rst_n = 1;
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#10;
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dut_ifc.a = 8'h35;
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dut_ifc.b = 8'h42;
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dut_ifc.doAdd0 = 1'b1;
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#20;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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$display("[%0t] Initial rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b",
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$time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b,
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dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow);
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$monitor("[%0t] Monitor rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b",
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$time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b,
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dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow);
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end
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endmodule
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