71 lines
1.9 KiB
Systemverilog
71 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer seeda;
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integer seedb;
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integer seedc;
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int valuea;
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int valueb;
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int valuec;
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int igna;
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int ignb;
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int ignc;
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initial begin
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// $random unlike $urandom updates the value if given
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seeda = 10;
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valuea = $random(seeda);
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seedb = 10;
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valueb = $random(seedb);
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if (valuea !== valueb) $stop;
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seeda = 10;
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valuea = $random(seeda);
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seedb = seeda;
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valueb = $random(seedb);
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seedc = seedb;
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valuec = $random(seedc);
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if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
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if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64
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valuea = $urandom(10);
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valueb = $urandom(10);
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valuec = $urandom(10);
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if (valuea !== valueb && valueb != valuec) $stop;
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valuea = $urandom(10);
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valueb = $urandom(11);
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valuec = $urandom(12);
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if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
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$urandom(10);
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valuea = $urandom;
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$urandom(10);
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valueb = $urandom;
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$urandom(10);
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valuec = $urandom;
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if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
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igna = $urandom(10);
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valuea = $urandom;
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ignb = $urandom(10);
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valueb = $urandom;
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ignc = $urandom(10);
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valuec = $urandom;
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if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
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valuea = $urandom(10);
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valueb = $urandom();
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valuec = $urandom();
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if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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