44 lines
1.0 KiB
Systemverilog
44 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(args) $write args
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`else
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`define WRITE_VERBOSE(args)
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`endif
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module t;
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logic clk = 0;
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always #3 clk = ~clk;
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logic flag_a;
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logic flag_b;
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always @(posedge clk)
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begin
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`WRITE_VERBOSE(("[%0t] b <= 0\n", $time));
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flag_b <= 1'b0;
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#2
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`WRITE_VERBOSE(("[%0t] a <= 1\n", $time));
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flag_a <= 1'b1;
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#2
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`WRITE_VERBOSE(("[%0t] b <= 1\n", $time));
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flag_b <= 1'b1;
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end
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always @(flag_a) if ($time > 0)
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begin
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#1
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`WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time));
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if (flag_b !== 1'b0) $stop;
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#2
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`WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time));
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if (flag_b !== 1'b1) $stop;
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#10
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #20 $stop; // timeout
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endmodule
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