47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 10ns / 1ns
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(args) $write args
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`else
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`define WRITE_VERBOSE(args)
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`endif
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module t;
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logic clk = 0;
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logic clk_copy;
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int cyc = 0;
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int cnt1 = 0;
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int cnt2 = 0;
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initial forever #1 clk = ~clk;
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always @(negedge clk) begin
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#0.75 cnt1++;
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`WRITE_VERBOSE(("[%0t] NEG clk (%b)\n", $time, clk));
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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#0.5 `WRITE_VERBOSE(("[%0t] POS clk (%b)\n", $time, clk));
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if (cyc == 5) begin
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if (cnt1 != 4 && cnt2 != 9) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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assign clk_copy = clk;
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always @(posedge clk_copy or negedge clk_copy) begin
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#0.25 cnt2++;
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`WRITE_VERBOSE(("[%0t] POS/NEG clk_copy (%b)\n", $time, clk_copy));
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end
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initial #100 $stop; // timeout
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endmodule
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