62 lines
1.5 KiB
Systemverilog
62 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int counter = 0;
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// As Verilator doesn't support recursive calls, let's use macros to
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// generate tasks for a deep call stack
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`ifdef TEST_VERBOSE
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`define DEEP_STACK_DELAY_END(i) \
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task delay``i; \
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counter++; \
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$write("[%0t] at depth %0d\n", $time, i); \
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counter++; \
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endtask
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`define DEEP_STACK_DELAY(i, j) \
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task delay``i; \
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$write("[%0t] entering depth %0d\n", $time, i); \
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#1 delay``j; \
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counter++; \
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#1 $write("[%0t] leaving depth %0d\n", $time, i); \
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counter++; \
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endtask
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`else
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`define DEEP_STACK_DELAY_END(i) \
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task delay``i; \
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counter += 2; \
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endtask
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`define DEEP_STACK_DELAY(i, j) \
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task delay``i; \
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#1 delay``j; \
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counter++; \
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#1; \
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counter++; \
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endtask
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`endif
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`DEEP_STACK_DELAY_END(10);
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`DEEP_STACK_DELAY(9, 10);
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`DEEP_STACK_DELAY(8, 9);
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`DEEP_STACK_DELAY(7, 8);
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`DEEP_STACK_DELAY(6, 7);
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`DEEP_STACK_DELAY(5, 6);
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`DEEP_STACK_DELAY(4, 5);
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`DEEP_STACK_DELAY(3, 4);
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`DEEP_STACK_DELAY(2, 3);
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`DEEP_STACK_DELAY(1, 2);
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initial begin
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delay1;
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if ($time != 9*2) $stop;
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if (counter != 10*2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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