34 lines
853 B
Systemverilog
34 lines
853 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module tb2 ();
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parameter CLK_PERIOD = 2;
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reg clk = 1'b0;
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int messages;
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always #(CLK_PERIOD / 2) clk = ~clk;
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always begin
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int counter = 0;
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while (counter < 3) begin
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counter += 1;
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$display("[%0t] Running loop %0d", $time, counter);
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messages += 1;
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@(posedge clk);
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end
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$write("[%0t] *-* All Finished *-*\n", $time);
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$finish;
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end
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final `checkd(messages, 3);
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endmodule
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