44 lines
935 B
Systemverilog
44 lines
935 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int counter = 0;
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// As Verilator doesn't support recursive calls, let's use macros to generate tasks
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`define FORK2_END(i) \
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task fork2_``i; \
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#1 counter++; \
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endtask
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`define FORK2(i, j) \
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task fork2_``i; \
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fork \
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#1 fork2_``j; \
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#1 fork2_``j; \
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join \
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endtask
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`FORK2_END(0);
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`FORK2(1, 0);
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`FORK2(2, 1);
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`FORK2(3, 2);
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`FORK2(4, 3);
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`FORK2(5, 4);
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`FORK2(6, 5);
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`FORK2(7, 6);
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`FORK2(8, 7);
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initial begin
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fork2_8;
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`ifdef TEST_VERBOSE
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$write("[%0t] process counter == %0d\n", $time, counter);
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`endif
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if (counter != 1 << 8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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