42 lines
934 B
Systemverilog
42 lines
934 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer cyc = 0;
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reg [7:0] a;
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reg [127:0] b;
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always #1 begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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a <= 8'hFF;
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a[7] <= 1'b0;
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end
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else if (cyc == 1) begin
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`ifdef TEST_VERBOSE
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$write("a = %x\n", a);
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`endif
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if (a != 8'h7F) $stop;
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end
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else if (cyc == 2) begin
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b <= 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
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b[127] <= 1'b0;
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end
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else if (cyc == 3) begin
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`ifdef TEST_VERBOSE
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$write("b = %x\n", b);
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`endif
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if (b != 128'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) $stop;
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end
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else if (cyc > 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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