45 lines
1.1 KiB
Systemverilog
45 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk1 = 0, clk2 = 0, clk3 = 0, clk4 = 0;
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always #2 clk1 = ~clk1;
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assign #1 clk2 = clk1;
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assign #1 clk3 = clk2;
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assign #1 clk4 = clk3;
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int x = 0;
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int cyc = 0;
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always @(posedge clk1) begin
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if (x != 0) $stop;
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`ifdef TEST_VERBOSE
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$display("[%0t] clk1 | x=%0d cyc=%0d", $realtime, x, cyc);
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`endif
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@(posedge clk2);
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`ifdef TEST_VERBOSE
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$display("[%0t] clk2 | x=%0d cyc=%0d", $realtime, x, cyc);
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`endif
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x <= x + 1;
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge clk3) begin
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`ifdef TEST_VERBOSE
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$display("[%0t] clk3 | x=%0d cyc=%0d", $realtime, x, cyc);
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`endif
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@(posedge clk4);
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`ifdef TEST_VERBOSE
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$display("[%0t] clk4 | x=%0d cyc=%0d", $realtime, x, cyc);
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`endif
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x <= x - 1;
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end
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endmodule
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