40 lines
922 B
Systemverilog
40 lines
922 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event e1;
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event e2;
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initial begin
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int x;
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// verilator timing_off
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#1
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fork @e1; @e2; join;
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@e1
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wait(x == 4)
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x = #1 8;
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// verilator timing_on
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if (x != 8) $stop;
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if ($time != 0) $stop;
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// verilator timing_off
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@e2;
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// verilator timing_on
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@e1;
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if ((e1.triggered && e2.triggered)
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|| (!e1.triggered && !e2.triggered)) $stop;
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if ($time != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #2 ->e1;
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// verilator timing_off
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initial #2 ->e2;
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// verilator timing_on
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initial #3 $stop; // timeout
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initial #1 @(e1, e2) #1 $stop; // timeout
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endmodule
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