36 lines
706 B
Systemverilog
36 lines
706 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event ping;
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event pong;
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int cnt = 0;
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initial forever @ping begin
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`ifdef TEST_VERBOSE
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$write("ping\n");
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`endif
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cnt++;
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->pong;
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end
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initial forever @pong begin
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`ifdef TEST_VERBOSE
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$write("pong\n");
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`endif
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if (cnt < 10) ->ping;
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end
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initial #1 ->ping;
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initial #2
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if (cnt == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end else $stop;
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initial #3 $stop; // timeout
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endmodule
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