verilator/test_regress/t/t_trace_no_top_name.out

$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module another_top $end
  $var wire 1 # b $end
 $upscope $end
 $scope module t $end
  $var wire 1 # a $end
 $upscope $end
$enddefinitions $end


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